By making the processing portion of the application go faster, a conventional memory system will be more of a drag on its performance. Memory bandwidth is also the performance bottleneck to fast programming of the re-configurable elements. That is why the IRAM group is working closely with the BRASS (Berkeley Re-configurable Architecture, Systems and Software) group, led by Prof. John Wawrzynek and Andre DeHon. It is a group at Berkeley that deals with all the Computer Architectures, and different systems and its software.
The first efforts of the IRAM project were started during the Spring 1996 offering of CS 294-4 at UC Berkeley. This advanced graduate course, led by Prof. David Patterson, examined the design of hardware and software that is based on the separation of the memory and the processor.
In early 1980s, Patterson and his colleagues pioneered RISC (Reduced Instruction-Set Computing), a technology that reformed microprocessor design and allowed small companies such as Sun and SGI to go in front of Intel. In 1987, Patterson helped develop RAID: a redundant array of disks that provides fast and cheap mass storage, which is used today in almost every large server. Now Patterson has begun this project on IRAM. The idea of putting a microprocessor into a memory chip is a move that may greatly improve computer performance.
Patterson's project for Intelligent RAM was motivated by one time that he had to write an article for the Scientific American. He started to think about the two greater bottlenecks in the computer industry right now: the memory and microprocessor industry. He then thought of a way to unite both, because the cost of the fabrication lines was getting very high also, and it wouldn't make sense to have two different fabrication lines for two things that are very alike. Once he started thinking about the possibility of combining memory and microprocessors, he realized that IRAM could solve the biggest problems facing computer creators.
