They also carefully designed the instruction set to be expandable to address new technologies and future workloads.
Architectural basics.
A historical problem facing the designers of computer architectures is the difficulty of building in sufficient flexibility to adapt to changing implementation strategies. For example, the number of available instruction bits, the register file size, the number of address space bits, or even how much parallelism a future implementation might employ have limited how well architectures can evolve over time.
The Intel-HP architecture team designed IA-64 to permit future expansion by providing sufficient architectural capacity: .
• a full 64-bit address space,.
• large directly accessible register files,.
• enough instruction bits to communicate information from the compiler to the hardware, and.
• the ability to express arbitrarily large amounts of ILP.
Register resources.
IA-64 provides 128 65-bit general registers; 64 of these bits specify data or memory addresses and 1 bit holds a deferred exception token or not-a-thing (N) bit. The "Control speculation- section provides more details on the N bit. In addition to the general registers, IA-64 contains.
• 128 82-bit floating-point registers,.
• space for up to 128 64-bit special-purpose .
• application registers (used to support features such as the register stack and software pipelining),.
• eight 64-bit branch registers for function call linkage and return, and .
• 64 one-bit predicate registers that hold the result of conditional expression evaluation.
Instruction encoding.
Since IA-64 has 128 general and 128 floating-point registers, instruction encodings use 7 bits to specify each of three register operands. Most instructions also have a predicate register argument that requires another 6 bits. In a normal 32-bit instruction encoding, this would leave only 5 bits to specify the opcode.
