PH317 Lab 4 - Components of Sequential Logic: Flip-Flops.
The objectives of this lab were to construct flip-flop circuits and understand their fundamental properties, add another capability to our test circuitry, examine and understand the fundamental properties of the 7473 dual JK F-F, the 7474 (positive-edge triggered D-type F-F) and the 7475 (latch), to design a state machine, and to construct and analyze a synchronizer and an asynchronous counter. .
Parts and Material Needed:.
• Breadboard with test circuitry .
• Logic probe .
• 7400 (quad NAND) .
• 7404 (hex inverter) .
• 7473 (dual JK FF) .
• 7474 (dual D FF) .
• 7475 (4 bit D Latch) .
• 555 (timer) .
• Pinouts for 7473,7474,7475 (in black binder at lab stations) .
• Engineering data sheet for 555 (in black binder at lab stations) .
1. R-S Flip Flop.
Procedure:.
We constructed an R-S F-F with two cross-coupled NAND gates. We used the DIP switches of our test circuitry for the R and S inputs. We monitored inputs with our logic state indicator (LED circuit) and the outputs with our logic probe. .
Analysis and Conclusion:.
We tested the R-S F-F under all possible combinations of input data and from this constructed the state table shown below.
R S Q Q`.
0 0 1 1.
1 0 0 1.
0 1 1 0.
The state where R and S are both high is not shown because that is a disallowed state. The values of Q and Q` are unpredictable.
When both inputs are grounded and then set to high at exactly the same time, the circuit is placed under race conditions, and whichever NAND gate's propagation time is less determines which output remains low. We determined from examining the circuit that whichever NAND switches high first, the corresponding output stays low.
2. Clock Circuit.
Procedure:.
We constructed a 1KHz timer with a duty cycle of about 25% using a 555 timer chip and an inverter. We built this circuit near our other test circuits as we will be leaving it in place for the rest of the semester.